1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having a step of forming electrode pins (pin-shaped electrodes) on a semiconductor chip using an electrode-pin forming mask, the semiconductor device, the electrode-pin forming mask and a method for testing the semiconductor chip using the electrode-pin forming mask, all of which can be suitably applied to a flip-chip-bonding mounting method, or the like.
Recently, a computer system which is miniaturized, capable of a high-speed operation performance, and has a high mounting density has been demanded by the public. As a result, it is required that a manufacturing technique enabling realization of a fine-pitch multi-electrode-pin arrangement in a semiconductor device be established in order to achieve miniaturization of semiconductor devices. Further, it is necessary that costs required for achieving the above demands be kept low. The above-mentioned fine-pitch multi-electrode-pin arrangement in a semiconductor device is an arrangement in which many electrode pins are finely arranged in a semiconductor device.
Mounting methods for fulfilling such demands, that is, a flip-chip-bonding mounting method and TAB (tape-automated-bonding) mounting method, have been made practicable. In these methods, it is necessary to previously form projecting electrodes on a semiconductor chip. Various construction types of such projecting electrodes have been proposed. One of the construction types is an electrode-pin type. The electrode-pin type of projecting electrodes is formed of micro-pins and will be referred to as electrode pins. In order to miniaturize semiconductor devices and also to keep the costs thereof low, it is necessary to form such electrode pins with high accuracy on the semiconductor chips and at a low cost.
2. Related Art
In the flip-chip-bonding mounting method using the electrode pins in the related art, a semiconductor chip is mounted on a mounting substrate by forming electron pads on either one of the semiconductor chip and the mounting substrate. On the pads, electrode pins are formed vertically and the thus formed electrode pins are bonded with the other one of the semiconductor chip and the mounting substrate. A wire-bonding method or a jig-used method is, in general, used for the formation of electrode pins on the pads.
The wire-bonding method will now be described. A wire-bonding apparatus is used in the method. One end of each of a number of gold wires is bonded on a respective one of the electrode pads formed on either one of the semiconductor chip and mounting substrate. Then, capillaries for supplying the gold wires are moved away from the electrode pads vertically by a predetermined distance so as to make each of the gold wires stand vertically on the electrode pads. Then, a spark rod is used to spark-cut the gold wires so that vertically standing gold wires remain on the electrode pads. The thus remaining gold wires are the electrode pins. Instead of using the spark rod, it is also possible to use a wedge to cut the gold wires.
The above-mentioned jig-used method (which may be referred to as `jig-used electrode-pin-forming method`, hereinafter) will now be described Previously, a number of electrode pins having a necessary length are manufactured and a jig is prepared. The jig has inserting-holes formed therein so that each of the positions of the inserting-holes therein can match a respective one of the electrode pads on which the electrode pins will be vertically formed. Then, the jig is loaded on either one of the semiconductor chip or mounting substrate, on which one the electrode pads were previously formed. The loading is performed so that each of the positions of the inserting holes of the jig matches a respective one of the electrode pads. Then, the previously manufactured number of electrode pins are put on the jig and the jig is vibrated using a vibration-applying machine, or the like. The vibration of the jig causes electrode pins put on the jig to be inserted into the inserting holes of the jig. Then, after all of the inserting holes have the electrode pins inserted therein, a heating process is performed on the electrode pins so that the electrode pins are heat-bonded on the electrode pads. Then, by removing the jig from the above-mentioned either one of the semiconductor chip and mounting substrate, the electrode pins remain vertically standing on the electrode pads.
Further, a testing step is included in the semiconductor device manufacturing process, the testing step testing whether or not the manufactured semiconductor chip performs predetermined operations. The testing step uses a testing apparatus, probe pins provided in the testing apparatus coming into contact with the electrode pins formed on the electrode pads so as to establish an electric contact between the probe pins and the electrode pins. The testing apparatus supplies a power source and testing signals to the semiconductor chip through the thus established electric contact. Thus, the above-mentioned testing of the semiconductor chip is performed.
There are problems in the above-mentioned semiconductor device manufacturing method. Specifically, in the above-described wire-bonding method, a gold wire is bonded on each of the electrode pads as described above. The number of the electrode pads provided is large to realize the above-mentioned fine-pitch multi-electrode-pin arrangement in the semiconductor device and thus much time is required for the relevant wire-bonding process. Therefore, production efficiency in the semiconductor device manufacturing using the wire-bonding method is low. Further, the length of the electrode pins depends on how long each of the gold wires is cut in the wire-bonding method. However, in the gold-wire cutting, the spark rod or wedge is used. Thus, accuracy with which the gold-wires are cut is low. As a result, the thus cut electrode pins formed on the electrode pads have lengths (heights) different from one another. Such electrode pins having different lengths may not ensure that electric contact is made between the electrode pins and other electrodes when the semiconductor chip is mounted on the mounting substrate.
Further, in realization of the above-mentioned fine-pitch multi-electrode-pin arrangement in the semiconductor device, the above-described jig-used electrode-pin-forming method is problematic. That is, it is not easy to actually insert the electrode pins in all of the inserting holes formed in the jig since it is necessary that each of the electrode pins consists of a small-diameter micro-pin to realize the above-mentioned fine-pitch multi-electrode-pin arrangement in the semiconductor device. Further, it is required that the jig appropriate for the realization of the fine-pitch multi-electronic-pin arrangement in the semiconductor device be manufactured with high accuracy and thus is expensive. Therefore, production efficiency using the jig-used method is low and the production costs are high.
Further, there are problems in the above-described testing step in realization of the fine-pitch multi-electrode-pin arrangement in the semiconductor device. Specifically, the above-described testing step in which the probe pins of the testing apparatus come into contact with the electrode pins directly has problems. This is because each of the probe pins in the ordinary testing apparatus has an outer diameter which is not small enough to match the above-mentioned fine-pitch multi-electrode-pin arrangement of the semiconductor device. That is, if many electrode pins are closely arranged over the entire surface of the semiconductor chip (, such an arrangement may be referred to as `closely-arranged electrode-pin arrangement`, hereinafter), since the diameter of each of the probe pins is not small enough, it is not possible to arrange the probe pins so as to make the probe-pin arrangement match the closely-arranged electrode-pin arrangement of the semiconductor chip. That is, it is not possible to make a pitch between adjacent probe pins of the testing apparatus small enough so it is made the same as a pitch between adjacent electrode pins on the semiconductor chip. Therefore, if the above step for testing the performance of the semiconductor chip is performed on the semiconductor device having the thus closely-arranged electrode-pin arrangement, the probe pins of the ordinary testing apparatus cannot be used. Instead, it is necessary to use an expensive special jig, or the like, for the purpose, thus causing the testing efficiency to be low and thus the production costs to be accordingly high.